4 Output 3.3V PCIe Zero-Delay 85Ohms Clock Buffer
| Pin | Name | Type |
|---|---|---|
| 5 | CLKIN | input |
| 6 | ~{CLKIN} | input |
| 12 | ~{OE0} | input |
| 19 | ~{OE1} | input |
| 24 | ~{OE2} | input |
| 29 | ~{OE3} | input |
| 9 | SCLK_3.3 | input |
| 10 | SDATA_3.3 | bidirectional |
| 1 | HIBW_BYPM_LOB | input |
| 31 | ~{CKPWRGD_PD} | input |
| 32 | SADR_tri | input |
| 15 | VDDO3.3 | power_in |
| 25 | VDDO3.3 | power_in |
| 21 | VDDA3.3 | power_in |
| 4 | VDDR3.3 | power_in |
| 11 | VDDDIG3.3 | power_in |
| 13 | DIF0 | output |
| 14 | ~{DIF0} | output |
| 17 | DIF1 | output |
| 18 | ~{DIF1} | output |
| 22 | DIF2 | output |
| 23 | ~{DIF2} | output |
| 27 | DIF3 | output |
| 28 | ~{DIF3} | output |
| 2 | FB_DNC | passive |
| 3 | ~{FB_DNC} | passive |
| 7 | NC | passive |
| 16 | NC | passive |
| 20 | NC | passive |
| 26 | NC | passive |
| 30 | NC | passive |
| 33 | GND | power_in |
| 8 | GNDDIG | power_in |
