32-Bit, 10 kSPS, Sigma-Delta ADC with 100 µs Settling and True Rail-to-Rail Buffers
| Pin | Name | Type |
|---|---|---|
| 21 | AIN0 | input |
| 22 | AIN1 | input |
| 23 | AIN2 | input |
| 24 | AIN3 | input |
| 1 | AIN4 | input |
| 3 | REF+ | input |
| 2 | REF- | input |
| 4 | REFOUT | output |
| 5 | REGCAPA | output |
| 7 | AVDD1 | power_in |
| 8 | AVDD2 | power_in |
| 6 | AVSS | power_in |
| 9 | XTAL1 | input |
| 10 | XTAL2/CLKIO | bidirectional |
| 14 | ~{CS} | input |
| 13 | SCLK | input |
| 12 | DIN | input |
| 11 | DOUT/~{RDY} | output |
| 15 | ~{SYNC}/~{ERR} | bidirectional |
| 19 | GPIO0 | bidirectional |
| 20 | GPIO1 | bidirectional |
| 18 | REGCAPD | output |
| 16 | IOVDD | power_in |
| 17 | DGND | power_in |
