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ADCLK944

2.5V/3.3V, Four LVPECL Outputs, SiGe Clock Fanout Buffer

ADCLK944VTCLK~{CLK}VCCVCCVEEVEEEPVREFQ0~{Q0}Q1~{Q1}Q2~{Q2}Q3~{Q3}

Pin Configuration (17 pins)

PinNameType
3VREFoutput
2VTinput
1CLKinput
4~{CLK}input
8VCCpower_in
13VCCpower_in
5VEEpower_in
16VEEpower_in
17EPpower_in
15Q0output
14~{Q0}output
12Q1output
11~{Q1}output
10Q2output
9~{Q2}output
7Q3output
6~{Q3}output

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Details

Librarycern-symbols
Pin Count17